In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETS) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the electrical performance of the device.
Thin channel silicon-on-insulator (SOI) devices are a promising option to further continue SOI complementary metal oxide semiconducting (CMOS) device scaling. Ultra-thin silicon channel devices provide a sharper sub-threshold slope (measure of the abruptness of the switching of the device), higher mobility, and better short channel effect control than silicon-on-insulator devices having a conventional thick channel.
A disadvantage of thin silicon channel devices is that as the SOI film is thinned the series resistance increases. One solution to the increasing series resistance inherent in thin channel devices is the use of elevated source/drain regions that may be formed by selective epitaxial silicon growth.
In prior thin channel devices, the extension implants are implanted prior to the formation of the raised source/drain regions; creating at least the following problems. By implanting the thin silicon layer using a high dose and high-energy implant, the silicon crystal layer can be amorphized. Additionally, during activation of the source/drain regions, the anneal processing step causes re-crystallization of the amorphous layer, which can result in the formation of polysilicon and the introduction of defects to the thin channel region resulting in a high resistivity. In addition, it is also difficult to clean the surfaces when P-type regions are formed due to electrochemical reactions since the P-type material has a greater affinity for oxide material and thus requires intensive surface preparation. The epitaxial growth process requires a clean surface having a crystalline structure. Therefore, it is highly desirable to provide a device that overcomes the above limitations.
Moreover, prior art thin ultra-small gate-length devices require an offset spacer for the formation of P-FET extension regions resulting in a high resistance region formed beneath the spacer. The silicon region directly outside the channel is thinner than the channel thickness underlying the gate stack due to over-etching during gate stack processing. When the offset spacer is deposited over the thin silicon region, a high resistance region is formed which limits device performance. The spacer dimension is directly related to resistance. Larger spacers cause higher resistance. Furthermore, since the extension implants are formed prior to the raised source/drain regions, they are subjected to the significant thermal budget of the raised source/drain process, which results in the unwanted diffusion of the dopant species. Typical raised source/drain process temperature is about 850° C., which is enough to cause significant diffusion. Another problem with the raised source/drain process is that the high temperature causes dopant loss since the Si surface is not protected during the growth process. Dopant loss also contributes to high resistance since the dopant is needed to make the semiconductor conductive. Adding a greater dose of the dopant species to compensate for the dopant loss further aggravates the diffusion problem since a greater dose of the dopant species is well known to cause greater diffusion of the dopants.
Additionally, the surfaces of P-type doped regions and N-type doped regions have different epitaxial growth rates, because the incubation time for epitaxial growth of raised source/drains on P-type doped regions differs from the incubation time for the epitaxial growth of raised source/drains on N-type doped regions. The difference in epitaxial growth rate can result in a substantially different raised source/drain thickness for the P-type and N-type regions, when processing both regions using the same incubation time. Finally, the surface concentration of the dopants must be uniform across the wafer as well as from wafer to wafer, which is a major challenge for manufacturing.
In one prior art thin channel device, a wide disposable spacer is utilized to grow the raised source/drain regions. High-energy implants are then performed to form deep source/drain regions. Following the source/drain implant, the wide disposable spacer is removed and the extension regions are implanted. The above prior art process overcomes excessive extension diffusion and the epitaxial Si growth rate differential between P-type and N-type regions, but does not overcome the formation of high resistance regions outside the raised source/drain area which are key to the performance of ultra-thin SOI MOSFETs. The formation of high resistance regions outside the raised source/drain area is also cost ineffective.
It would be highly desirable to provide a thin channel CMOS device that overcomes the above described high resistance region and exposure to high thermal budgets during processing.